Memory systems typically comprise a plurality of Dynamic Random Access Memory (DRAM) integrated circuits, referred to herein as DRAM devices or chips, which are connected to one or more processors via one or more memory channels. On each chip or DRAM die, one or more DRAM banks are formed, which typically work together to respond to a memory request. Typically, in each bank, multiple arrays (also known as subarrays or mats) are formed, each array including a row buffer to act as a cache. Conventional DRAM architectures use a single row buffer for each array in the DRAM.
DRAM is considered dynamic in nature as DRAM cells lose their state over time periodically. Information stored in the rows and columns of the array is “sensed” by bit lines of the DRAM. In order to utilize bit lines in the DRAM, there must be a precharging process.
Based on the conventional DRAM architecture, there are several commands that are serialized due to the limitations of the DRAM design. Specifically, in DRAM bank precharging of bit lines, any precharge command cannot be overlapped with other operations. When scheduling the DRAM architectures, multiple commands, including precharging a row in the array or sensing a row into the single row buffer, are scheduled in a pipeline manner. However, the effective access latency is increased because of the required serialization of commands as a bottleneck is created in the pipeline. Write recovery latency becomes part of the critical path when switching rows after a write.
Thus, there is a need for concepts allowing the reduction of access latency and write recovery latency in DRAM architectures.